Memory Layout Engineer
Memory Layout Engineer
Posted on :
18-07-2025
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1 Vacancy
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Job Description
Job Title: Memory Layout Engineer
Job Location: Irvine/San Jose (CA) Minneapolis (MN) Phoenix/Chandler (AZ)
Job Location: Irvine/San Jose (CA) Minneapolis (MN) Phoenix/Chandler (AZ)
Job Duration: 3 Months Contract to Hire
Job Responsibilities:
- Design and implement custom memory layouts for advanced technology nodes collaborating with circuit designers to optimize performance power and area.
- Mitigate layout design effects such as N-well proximity effect diffusion spacing effect and length of diffusion effects.
- Collaborate with SoC partners to develop cutting-edge SRAM and Register File layout designs.
- Participate in design reviews to improve the quality of memory layouts.
- Stay up to date with the latest industry trends and developments in memory layout design.
- Perform physical verification (LVS DRC ANT etc.) and debug memory layout.
- Leading and mentoring junior layout engineers and providing guidance on layout techniques.
- The ability to adhere to project timelines to ensure deliveries are met according to project schedules.
- Effectively communicate with the design team to clarify and realize the layout requirements based on the schematic design intent.
- Must be able to effectively switch between manufacturing nodes with minimal ramp.
Qualifications:
- 7 years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3 years of recent experience on advanced nodes including FinFET technologies
- Great understanding of CAD flows and tools related to analog/mixed-signal layout design
- Excellent programming skills in languages: SKILL Perl; Python is a plus
- Strong fundamentals in software development
- Solid experience with EMIR (RV) Physical design verification (DRC/LVS/PEX/ERC) waiver
- Working knowledge of circuit design concepts such as device characteristics SPICE and Verilog netlists and simulation
- Excellent communication and interpersonal skills
Mandatory Skills:
- Synopsys/Cadence Analog Layout Tools (Preference: 5)
- Memory design and layout (Preference: 5)
- Python (Preference: 2)
Employment Type
Full-time
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