Engineering Leader â SoC Verification,Synopsys, Cadence, SystemVerilog
Engineering Leader â SoC Verification,Synopsys, Cadence, SystemVerilog
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Job Description
Role: Engineering Leader SoC Verification
Location: Redmond WA (Onsite)
Interview: Phone/Skype
Type: Contract
Were hiring a hands-on Engineering Leader to drive advanced SoC verification strategies and lead cross-functional collaboration. Must have expertise in #UVM #SystemVerilog #Synopsys #Cadence #Python #TCL #Perl and experience building test benches debugging designs and optimizing verification methodologies.
Additional Information :
All your information will be kept confidential according to EEO guidelines.
Remote Work :
No
Employment Type :
Contract
Employment Type
Contract
