RTL Engineer
RTL Engineer
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Salary Not Disclosed
1 Vacancy
Job Description
Role: Integrate RISC-V Core to SoC
Key Responsibilities
- Integrate RISC-V CPU cores into SoC designs collaborating with cross-functional teams (DV physical design architecture verification and post-silicon validation) to ensure seamless delivery.
- Develop and optimize RTL (using Verilog/SystemVerilog) for core interconnect and memory subsystems.
- Evaluate and integrate third-party IP ensuring performance power and area (PPA) targets are met.
- Debug complex RTL/logic issues across design hierarchies (core chip) in both pre-silicon and post-silicon environments.
- Enhance RTL design infrastructure tools and methodologies for improved efficiency and quality.
- Analyze synthesis timing and power results to drive design improvements.
Required Qualifications
- 5 years of experience in RTL design SoC integration or related areas.
- Strong hands-on experience with hardware description languages (Verilog SystemVerilog VHDL) EDA tools and simulators (VCS NC Verilator).
- Deep understanding of SoC design integration and high-performance interfaces (e.g. AXI TileLink PCIe Ethernet).
- Proven ability to debug and optimize designs for functional timing and power convergence.
- Excellent problem-solving and communication skills.
Preferred Skills
- Experience with RISC-V architecture and integrating RISC-V cores into SoCs.
- Familiarity with cache coherence protocols memory ordering models and interconnect topologies.
- Scripting (Python Tcl) for automation and flow development.
Employment Type
Full-time
