Principal UVM Digital Verification Engineer

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Job Description Summary:

Job Description:

Duties/Responsibilities
Independently drive solutions to complex problems - develop requirements propose ways forward when customer requirements are unclear or incomplete and adapt appropriately to changes in requirements.
Subject Matter Expert (SME) in Systems Engineering
Provide insight and suggest design modifications based on analysis outcomes and to apply analysis techniques across a range of technical challenges and disciplines
Identify program/system-level technical risks and develop and execute mitigation strategies.
Develop document and teach best practices to less experienced engineers
Actively mentors. Recognizes strengths and weaknesses in others and provides thoughtful constructive feedback.
Work in a collaborative multidisciplinary environment including stakeholders and external partners.
Contribute to translation of requirements into technical and architectural decisions.
Identify and develop relevant modeling and analysis techniques and develop or integrate multi-domain qualitative models.
Present results that support system-level analysis performance trade-offs and real-time decision-making.
Communicate technical concepts effectively with customers engineers managers and other stakeholders of all relevant disciplines.

Skills/Abilities
Excellent mathematical skills.
Thorough understanding of engineering theories and procedures.
Ability to collaborate within a diverse and multidisciplinary team.
Excellent verbal and written communication skills.
Excellent organizational skills and attention to detail.
Excellent time management skills with the proven ability to meet deadlines.
Demonstrate strong organization planning and time management skills to achieve program goals.
Demonstrated knowledge of multiple problem domains.
Multi-task and adapt to evolving priorities.
Ability to quickly become knowledgeable in new domains.

Education
Bachelors degree in Aerospace Electrical Mechanical or other relevant Engineering field. Masters degree preferred.

Experience
Requires 7-10 years experience in systems analysis or related.
Experience in use of MBSE tools such as SysML knowledge in MATLAB/Simulink.
Experience in integrating descriptive modeling tools with other simulation tools.

Additional Job Description:

You will develop verification approaches author and execute verification plans and use formal analysis tools. While leading verification teams you will define the test-bench architecture and verification approach. You will be responsible for developing methodologies and defining processes used by verification teams. You will also have the opportunity to lead multi-disciplinary teams and learn grow and contribute to a variety of projects. Join us as we develop the next generation of digital and embedded hardware platforms.

• Fluent in System Verilog including SVA
• Familiarity with at least one major industry simulator (Questasim Xcelium VCS)
• Familiarity with at least one IEEE bus standard
• Experience with DDR3/DDR4 Amba Axi protocols
• Firm grasp of constrained-random testing and coverage-driven verification
• Experience with formal analysis
• Practice using Python Perl Bash or other scripting languages
• Ability to work in a Linux environment
• Strong analysis and problem-solving skills
• Develop verification and test plans
• Develop UVM Agents for proprietary buses
• Instantiate VIPs for industry standard buses
• Work in both block-level/chip-level UVM testbench environment
• Work with RTL designers to resolve simulation issues
• Implement cover groups according to design requirements
• Work on code and functional coverage closures to achieve 100%
• Perform code reviews and to mentor junior engineers in the group

Applicants selected for this position will be required to obtain and maintain a government security clearance.