Physical Design Engineer
Physical Design Engineer
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Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
- Pre-layout STA to ascertain feasibility timing constraint validation and feedback to customers and design teams
- Chip/Block Level Floorplanning and pin assignment
- Review top-level/block-level clock specifications for completeness and feasibility
- Handle all the Physical design tasks (Placement Timing Optimization Clock Tree Synthesis Routing)
- Perform sign-off tasks (RC Extraction Static Timing Analysis IR drop analysis and Physical Verification)
- Presentations and Customer Interaction in customer meetings
- BSEE with 5 years of experience or equivalent experience. MSEE preferred.
- Experience in ASIC Physical Design; Experience in a SoC product development organization with tape outs at 28nm/16nm design nodes and lower.
- Hands-on Experience with implementation EDA tools like ICC2/Innovus.
- Scripting (Perl/Tcl/Python) is required.
- Good understanding of ASIC frontend design.
- Experience in both Flat and Hierarchical layouts.
- Strong problem-solving skills and ability to analyze and resolve physical design issues related to library timing constraints or CAD tools is required.
- Experience with power analysis and IR-drop tools (prime power/Redhawk) and Static Timing Analysis (Primetime).
- Experience with Physical Verification and fix PV errors in layout.
- Expert handling of Verilog HDL based Netlists Physical design libraries.
- Team player with good interpersonal and communication skills; ability to explain processes and answer customer questions during meetings.
Employment Type
Full Time
