Principal Engineer, Physical Design
Principal Engineer, Physical Design
Employer Active
Job Alert
You will be updated with latest job alerts via email
Share
Job Alert
You will be updated with latest job alerts via email
Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
About Marvell
Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.
At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.
Your Team Your Impact
Built on decades of expertise and execution Marvells custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role youll have the opportunity to work on both the physical design and methodology for future designs of our next-generation high-performance processor chips in a leading-edge CMOS process technology targeted at server 5G/6G automotive and networking applications.What You Can Expect
For senior engineering candidates seeking a challenging and impactful role this position at Marvell involves spearheading enhancements and providing critical support for our sophisticated Place and Route Flow seamlessly incorporating industry-standard EDA tools. Your responsibilities encompass performing synthesis place and route as well as conducting in-depth timing analysis and closure on multiple complex and expert-level logic blocks. You will be at the forefront of developing and implementing intricate timing and logic ECOs. Collaboration is key and you will work closely with the RTL design team to drive modifications that effectively resolve congestion and timing issues. Engaging with the global timing team your role extends to debugging and resolving block-level timing issues observed at the partition level or full chip. Moreover your influence will extend to interactions with tool vendors where youll drive improvements and conduct evaluations of new tools and functions. This role presents an exciting opportunity for seasoned engineers to contribute to cutting-edge projects in a collaborative and innovative environment at Marvell.
What Were Looking For
Bachelors degree in Computer Science Electrical Engineering or related fields and 10-15 years of related professional experience OR Masters degree and/or PhD in Computer Science Electrical Engineering or related fields with 5-10 years of experience. In your coursework you must have completed a digital logic course and projects that involved circuit design testing and timing analysis.
Strong understanding of standard RTL to GDS flows and methodology.
Strong scripting skills in languages such as Perl tcl and Python.
Strong object-oriented programming skills.
In-depth understanding of digital logic and computer architecture.
In-depth knowledge of Verilog/VHDL.
Good communication skills and self-discipline contributing in a team environment.
Expected Base Pay Range (USD)
146850 - 220000 $ per annumThe successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell we offer a total compensation package with a base bonus and and financial wellbeing are part of the package. That means flexible time off 401k plus a year-end shutdown floating holidays paid time off to volunteer. Have a question about our benefits packages - health or financial Ask your recruiter during the interview process.All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .
#LI-VM1Required Experience:
Staff IC
Employment Type
Full Time
