Senior UVM Digital Verification Engineer Hybrid
Senior UVM Digital Verification Engineer Hybrid
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5years
$ 160000 - 190000
1 Vacancy
Job Description
Key Responsibilities
Develop verification and test plans for digital and mixed-signal designs
Build and maintain UVM agents and instantiate VIPs for standard/proprietary buses
Execute block-level and chip-level UVM testbenches
Collaborate with RTL designers to resolve simulation issues
Implement and manage cover groups to meet 100% functional/code coverage
Lead small teams and mentor junior engineers
Analyze technical risks and contribute to system engineering lifecycle activities
Translate system requirements into architectural and design decisions
Support integration and test activities in a multidisciplinary environment
Requirements
Technical Requirements
Fluent in SystemVerilog including SystemVerilog Assertions (SVA)
Deep experience with UVM/UVMF and industry simulators (e.g. Questasim Xcelium VCS)
Knowledge of protocols such as AXI DDR3/DDR4
Proficiency with scripting languages (e.g. Python Perl Bash)
Strong background in constrained-random testing and coverage-driven verification
Familiarity with formal analysis tools
Comfortable working in Linux environments
General Skills
Excellent mathematical and problem-solving skills
Strong written and verbal communication skills
Demonstrated ability to mentor and collaborate across teams
Ability to work independently and manage changing priorities
Skilled in using MBSE tools (e.g. SysML) and simulation platforms (MATLAB/Simulink)
Education & Experience
Bachelors degree in Aerospace Electrical Mechanical or related engineering field (Master s preferred)
5 15 years of experience in digital verification system analysis or a related field
Experience integrating modeling tools and developing multi-domain models
Additional Requirements
Applicants must be U.S. citizens or permanent residents
Must be able to obtain and maintain a government security clearance
Job Details
Experience Required: 5 15 years
Work Schedule: Full-time hybrid (3 days in office)
Location: Cambridge MA
Number of Openings: 1
Technical Requirements Fluent in SystemVerilog, including SystemVerilog Assertions (SVA) Deep experience with UVM/UVMF and industry simulators (e.g., Questasim, Xcelium, VCS) Knowledge of protocols such as AXI, DDR3/DDR4 Proficiency with scripting languages (e.g., Python, Perl, Bash) Strong background in constrained-random testing and coverage-driven verification Familiarity with formal analysis tools Comfortable working in Linux environments General Skills Excellent mathematical and problem-solving skills Strong written and verbal communication skills Demonstrated ability to mentor and collaborate across teams Ability to work independently and manage changing priorities Skilled in using MBSE tools (e.g., SysML) and simulation platforms (MATLAB/Simulink) Education & Experience Bachelor's degree in Aerospace, Electrical, Mechanical, or related engineering field (Master s preferred) 5 15 years of experience in digital verification, system analysis, or a related field Experience integrating modeling tools and developing multi-domain models Additional Requirements Applicants must be U.S. citizens or permanent residents Must be able to obtain and maintain a government security clearance Job Details Experience Required: 5 15 years Work Schedule: Full-time, hybrid (3+ days in office) Location: Cambridge, MA Number of Openings: 1
Employment Type
Full Time
