Senior Principal Engineer
Senior Principal Engineer
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Job Description
About Marvell
Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.
At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.
Your Team Your Impact
The Data Centre Engineering Group develops Custom Silicon products tailored for the Data Centre market focusing on cutting-edge Accelerated Infrastructure solutions for Networking Switching Connectivity and Compute. The team works on high-performance and scalable architectures ensuring optimized performance power efficiency and reliability to meet evolving data center demands. By collaborating across multiple teams the group delivers best-in-class silicon solutions that drive innovation in next-generation data center applications.What You Can Expect
- Lead the DV execution and sign-off for the entire SoC
- Define and drive improvements in DV processes for efficient and high-quality execution
- Collaborate with IP Subsystem and SoC teams on test plan creation testbench architecture and milestone reviews
- Work closely with Design and DV teams across IP Subsystem and SoC levels for test plan development execution debug coverage closure and gate-level simulations
- Coordinate with cross-functional teams including Architecture Chip Lead Emulation and Program Management to drive SoC-level DV execution
- Partner with Silicon bring-up and Firmware teams to support post-silicon validation and bring-up activities
- Own and debug simulation failures to identify and resolve root causes
- Architect and implement simulation testbenches using UVM
- Develop and execute test plans to verify design correctness and performance
- Collaborate with logic designers for thorough verification coverage and closure
What Were Looking For
- Bachelors degree in CS/EE with 22 years of relevant experience or Masters degree in CS/EE with 20 years of relevant experience
- Strong background in IP and SoC verification methodologies and testbench development using Verilog SystemVerilog UVM and C/C
- Deep understanding of verification techniques including object-oriented programming white-box/black-box testing directed/random testing formal verification coverage analysis and gate-level simulations
- Proven experience in DV sign-off for Functional Power Performance and Security metrics
- Strong knowledge of Unix/Linux environments; scripting experience in Shell Perl or Python is a plus
- Demonstrated analytical and problem-solving capabilities
- Ability to manage multiple tasks in a fast-paced dynamic environment
- Excellent interpersonal teamwork and communication skills
- Proven ability to interface across all levels of internal and external stakeholders
- Experience leading DV execution and sign-off for complex SoCs
- Hands-on involvement in 10 successful tape-outs and post-silicon bring-up
Additional Compensation and Benefit Elements
With competitive compensation and great benefits you will enjoy our workstyle within an environment of shared collaboration transparency and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters and to grow and develop with us. For additional information on what its like to work at Marvell visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.
#LI-KP1Required Experience:
Staff IC
Employment Type
Full-Time
