AE Director, Serdes Design IPs
AE Director, Serdes Design IPs
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$ 157500 - 292500
1 Vacancy
Job Description
At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is seeking a motivated detail oriented and creative individual to join the Worldwide IP Sales team as Applications Engineering Director for our Serdes IP Portfolio. The ideal candidate for this position is a seasoned High-Speed Interface Technologist who enjoys leading a team of skilled engineers and working with customers to develop solutions for their System/ASIC/SoC designs using the Cadence Serdes IP portfolio. This is a pre-sales role. It is perfect for someone who has System/ASIC/SoC design experience and great interpersonal and communication skills and is committed to the success of our customers. You will have an opportunity to work across various market segments (AI Cloud Networking Storage) designs foundries and leading/bleeding edge processes and build credibility in solving the toughest high-speed interface challenges.
Responsibilities include:
Leading a high performing team of senior application engineers on technical presales for Serial interface PHYs and controllers.
Developing appropriate strategies to win deals
Collaborating with the sales & marketing teams to identify and understand the technical and business challenges of our customers.
Developing solutions for customers leveraging the broad Cadence IP portfolio.
Educating our customers on how the IP products meet their needs and helping them evaluate the IP (with support from the product R&D teams) relative to their requirements.
Influencing the IP product development roadmap by communicating customer needs to the product R&D teams.
Keeping up with industry trends and protocol evolutions at PCI-SIG and other standards bodies.
Managing and supporting the engagements via on-site or remote technical interactions providing demos supporting evaluations resolving technical problems addressing competitive challenges and regularly communicating status among cross functional teams.
Qualifications and Experience
MSEE with 15 years of relevant experience or PhD with 10 years of relevant experience.
Management experience leading a highly technical team.
Prior experience in selecting using designing or supporting PHY and controller interface IP internal or external
Understanding of latest SoC architectures and system-level design practices for market segments (mobile storage automotive networking IoT) particularly from IP requirements perspective
Prior experience and knowledge of one or more interface and connectivity protocols e.g. PCIe CXL UCIe Ethernet USB MIPI 112G 56G.
Familiarity with state-of-the-art SoC design implementation: RTL design synthesis and static timing analysis physical design flow testbench creation and simulation some familiarity with analog/mixed-signal design and verification flows and basic understanding of foundry package and PCB design flows and technologies
Ability to understand and present complex technical requirements problems and solutions concisely in verbal and written communications
Ability to organize conduct and co-ordinate meetings involving multiple teams internal and external
Travel ( 10%) required to visit customer sales and engineering locations
The annual salary range for California is $157500 to $292500. You may also be eligible to receive incentive compensation: bonus equity and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications skill level competencies and work location. Our benefits programs include: paid vacation and paid holidays 401(k) plan with employer match employee stock purchase plan a variety of medical dental and vision plan options and more.
Were doing work that matters. Help us solve what others cant.
Required Experience:
Director
Employment Type
Full-Time
