Overview
The Physical Design Engineer with PNR (Place and Route) expertise plays a critical role in the semiconductor industry responsible for transforming netlist descriptions into physical representations suitable for silicon fabrication. This position is fundamental for ensuring that chip designs meet performance area and power specifications. The role demands a blend of technical prowess creativity and problem-solving abilities to navigate complex design challenges. Engineers in this role must coordinate with cross-functional teams including digital design verification and fabrication to ensure seamless of design projects. By driving the physical design process and optimizing layouts using advanced tools the Physical Design Engineer ensures that the final design is both manufacturable and performant. With the ever-increasing complexity of integrated circuits this position is essential for enhancing product competitiveness and achieving timely market deliveries.
Key Responsibilities
- Develop detailed floor plans for chip designs adhering to engineering guidelines.
- Implement place and route methods to efficiently map nets on the silicon.
- Conduct timing analysis and optimization for performance objectives.
- Collaborate with design teams to ensure integration of DFT (Design For Test) techniques.
- Perform physical verification checks using tools to identify design rule violations.
- Optimize power performance and area (PPA) throughout the design process.
- Create and maintain detailed documentation for design specifications and methodologies.
- Conduct signal integrity analysis to mitigate performance issues.
- Coordinate with manufacturing teams to ensure design manufacturability.
- Participate in design reviews assessing the physical design aspects of projects.
- Adapt to new technologies and tools to enhance design capabilities.
- Resolving layout-level issues and implementing iterative improvements.
- Train and mentor junior design engineers in physical design processes.
- Analyze yield data and implement changes to improve manufacturability.
- Support post-layout verification and debug efforts for tapeout readiness.
Required Qualifications
- Bachelors or Masters degree in Electrical Engineering Computer Engineering or related field.
- 4 years of experience in physical design particularly using PNR methodologies.
- Proficiency in industry-standard EDA tools for physical design (e.g. Cadence Synopsys).
- Solid understanding of semiconductor physics and design processes.
- Experience with timing analysis tools and methods (e.g. PrimeTime).
- Familiarity with DFT methodologies and tools (e.g. Tetramax FastScan).
- Knowledge of signal integrity and low power design techniques.
- Strong problem-solving skills with the ability to work in a fast-paced environment.
- Excellent communication skills for effective collaboration with cross-functional teams.
- Ability to thrive under pressure and manage multiple projects simultaneously.
- Understanding of physical design challenges related to advanced technology nodes.
- Familiarity with scripting languages (e.g. TCL Perl) for automation.
- Experience with level shifters delay lines and analog design principles is a plus.
- Knowledge of design verification processes and tools is beneficial.
- Attention to detail and commitment to quality in all aspects of work.
- Willingness to continuously learn and adapt to industry advancements.
scripting (tcl, perl),signal integrity analysis,pnr,dft (design for test),eda tools (cadence, synopsys),physical design,timing analysis,layout design,communication,signal integrity,power, performance, area (ppa) optimization,design tools,pnr (place and route),physical verification,team collaboration,problem-solving