DV Engineer
DV Engineer
Posted on :
31-05-2025
Employer Active
1 Vacancy
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Job Description
Role - DV Engineer
Location: EU / Remote
Mandatory Skill:
- IP/ SOC verification
- Verilog System Verilog UVM
- Code Coverage functional coverage
Industry Experience : 5 to 10 years
- SOC Verfication Experience on ARM Ecosystem
- PCIE Experience and also PCIE-VIP usage experience
- GLS working experience
- Proficient in C/System Verilog and UVM
- Working knowledge of GIT
Employment Type
Full Time
Key Skills
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