5 to 8 years of experience Minimum BE/BS degree (Masters preferred) in Electrical/Electronics Engineering/VLSI with practical experience Strong fundamentals in digital ASIC design Expertise in ARM v8 and v9 specifications and their impact to SoC system architecture Multiple project experience with ARM based ecosystem components (Aseries ARM Cores SMMU GIC Coresight NIC and other complex bus interconnects) Familiarity with AMBA bus protocols system memory hierarchy system debug infrastructure and multicore SOC designs Exposure to ARM platform architecture specifications Strong experience with Verilog SystemVerilog DC/DCT based synthesis constraints development and RTL level checks. Low power methodology knowledge will be a plus. Understanding of major SOC interfaces like PCIE DRAM Flash I2C SSP UART. Capable of working with multiple IP vendors and other teams Excellent communication and leadership quality to lead design team
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