DFT Engineer

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge.


Work hard. Have fun. Make history.

We are seeking a skilled and handson DFT Engineer (Level 5) to contribute to the DesignforTest (DFT) implementation for SoCs. This role requires strong technical expertise in scan MBIST boundary scan STA closure and silicon readiness to support highvolume SoC products. You will work in a crossfunctional team environment alongside RTL physical design and test engineering teams.

Why This Role
As an L5 DFT Engineer you will play a critical handson role in defining and implementing DesignforTest (DFT) strategies for nextgeneration SoCs. This role offers you the opportunity to work at the heart of silicon development collaborating with architects RTL designers physical design and test engineering teams to ensure silicon is testable and productionready.

If youre a selfmotivated engineer who thrives in technically challenging environments and is passionate about highquality highcoverage test solutions this role is an ideal platform to balance of technical depth collaboration and impactful execution on real silicon products.


Key job responsibilities
Insert and verify DFT logic and components in subsystem RTL netlists. Enhance and improve DFT implementation to achieve DFT coverage targets. Review signoff level timing closure using static timing analysis of DFT mode. Generate and sign off highquality presilicon DFT patterns.

Education: BS/BE or MS/ME in Electrical/electronic or Computer Engineering or related discipline.

Experience:
Minimum 5 years in semiconductor industry as a DFT engineer

Technical Expertise:
Insert and verify DFT logic and components in subsystem RTL netlists. Enhance and improve DFT implementation to achieve DFT coverage targets. Generate and sign off highquality presilicon DFT patterns.

Scan / ATPG:
Handson experience in scan insertion and ATPG pattern generation for high fault coverage.
Debugging RTL/Gatelevel mismatches during scan simulation.
Experience with IEEE(IJTAG) for corelevel DFT integration.

MBIST / Memory Repair:
MBIST BISR and BIHR insertion tools and methodologies.
Familiarity with sharedbus MBIST architecture is a plus.
Experience in memory repair signature generation and validation.

Boundary Scan & IJTAG:
Working knowledge of IEEE 1149.x (Boundary Scan) and 1500 and 1687 IJTAG implementation.
IJTAG ICL extraction PDL modeling using Siemens Tessent (is a plus) or equivalent.

STA / Timing Closure:
Static timing analysis (STA) with DFT constraints for shift and capture paths.
DFTaware timing closure in collaboration with physical design teams.

Automation & Scripting:
Experience in developing automated workflows using Python Tcl or Perl.
Reusable scripts for DFT flow integration reporting and analysis.

Soft Skills & Collaboration:
Strong communication skills; ability to collaborate with RTL physical design test and PE teams.


Debug / PostSilicon:
Postsilicon DFT pattern validation and silicon debug.
Collaboration with ATE and Product Engineering teams for bringup and correlation.
Familiarity with failure triage using scan diagnosis tools.

Soft Skills:
Ability to work in a fastpaced evolving environment
Selfdriven detailoriented executionfocused.
Team player with the ability to work across international teams.


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