C SrManagerSr Architect - ASIC RTL 6-22 yrs Pan India
C SrManagerSr Architect - ASIC RTL 6-22 yrs Pan India
Posted on :
29-04-2025
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1 Vacancy
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Job Description
Job Opening: Senior Manager/Senior Architect ASIC RTL
Location: Pan India
Job Description:
We are seeking an experienced ASIC RTL Developer with a focus on RTL coding IP design and SoC development. The role entails responsibilities such as microarchitecture design RTL implementation and logic synthesis. The ideal candidate should possess strong skills in Lint CDC analysis and resolving design issues. Collaboration with architecture verification and physical design teams is essential to ensure the delivery of highquality silicon. Expertise in Verilog/SystemVerilog SOC integration and IP block development is crucial for this role.
Required Skills:
- Expertise in SoC subsystem/IP design
- Proficiency in IP design Subsystem/Cluster and SoC level integration using Verilog/System Verilog
- Indepth knowledge of RTL quality checks (Lint CDC)
- Familiarity with synthesis and low power is a plus
- Good understanding of AMBA bus protocols (AXI AHB ATB APB)
- Proficiency in timing concepts
- Knowledge of one or more interface protocols: PCIe DDR Ethernet I2C UART SPI
- Experience in setting up and using tools like Spyglass Lint/CDC Synopsys DC Verdi/Xcellium
- Understanding of scripting languages such as Make flow Perl shell Python etc.
- Familiarity with processor architecture and/or ARM debug architecture is advantageous
- Ability to assist and debug issues for multiple subsystems
- Capability to create/review design documents for multiple subsystems
- Support for physical design verification DFT and SW teams on design queries and reviews
Requirements
Requirements:
- 622 years of experience
- Proficiency in RTL Coding design IP design SOC Development Lint CDC Micro Architecture
Expertise in SoC subsystem/IP design Proficiency in IP design, Subsystem/Cluster, and SoC level integration using Verilog/System Verilog In-depth knowledge of RTL quality checks (Lint, CDC) Familiarity with synthesis and low power is a plus Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) Proficiency in timing concepts Knowledge of one or more interface protocols: PCIe, DDR, Ethernet, I2C, UART, SPI Experience in setting up and using tools like Spyglass Lint/CDC, Synopsys DC, Verdi/Xcellium Understanding of scripting languages such as Make flow, Perl, shell, Python, etc. Familiarity with processor architecture and/or ARM debug architecture is advantageous Ability to assist and debug issues for multiple subsystems Capability to create/review design documents for multiple subsystems Support for physical design, verification, DFT, and SW teams on design queries and reviews
Education
Any graduate or post graduate
Employment Type
Full Time
Key Skills
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