Hardware Engineer Design and Verification

Snapshot:

At Google DeepMind weve built a unique culture and work environment where longterm ambitious research can flourish. We are seeking a highly motivated Hardware Engineer to join our team and contribute to development of groundbreaking silicon for machine learning inference acceleration.

About us:

Artificial Intelligence could be one of humanitys most useful inventions. At Google DeepMind were a team of scientists engineers machine learning experts and more working together to advance the state of the art in artificial intelligence. We use our technologies for widespread public benefit and scientific discovery and collaborate with others on critical challenges ensuring safety and ethics are the highest priority.

About you:

We seek out individuals who thrive in ambiguity and who are willing to help out with whatever moves silicon design and architecture forward. We regularly need to invent novel solutions to problems and often change course if our ideas dont work out so flexibility and adaptability to work on any project is a must.

The Role:

We are seeking a talented and highly motivated hardware engineer to join our GenAI technical infrastructure research hardware team. You will have the opportunity to partake into cuttingedge architecture exploration that will shape the future of machine learning inference acceleration.

Responsibilities:

• High performance machine learning inference accelerator microarchitecture RTL design and verification.
• Creation and steering of the development of the RTL verification strategy.
• Facilitate design verification steer the verification planning and .
• Creation of alignment between RTL design and design verification engineering.

Minimum Qualifications:

• Bachelors degree in Electrical Engineering Computer Science or equivalent practical experience.
• 7 years of experience in RTL design and verification in Verilog/System Verilog.
• 5 years of experience in hardware microarchitecture definition.
• Knowledge of UVM libraries and testbench architectures.
• Experience from design and integration of complex highspeed IP such as PCIe DDR HBM.
• Experience with high performance compute IPs (e.g. GPUs DSPs or machine learning accelerators).
• Deep knowledge in evaluating tradeoffs such as speed performance power area.
• Good understanding of ASIC design flow including RTL design verification logic synthesis and timing analysis
• Handson knowledge of basic hardware requirements and building blocks of ML accelerators custom number formats matrix multiply units vector and elementwise computation etc.

Preferred Qualifications:

• Working experience developing with C & Python.
• Physical Design background or hands on experience.
• Knowledge/understanding of high level synthesis.
• Knowledge of high performance and low power architectures for ML acceleration.
• Working knowledge of transformerbased large language models.

The US base salary range for this fulltime position is between $156000 $229000 bonus equity benefits. Your recruiter can share more about the specific salary range for your targeted location during the hiring process.

Application deadline: 12pm PST Friday May 16th 2025

Note: In the event your application is successful and an offer of employment is made to you any offer of employment will be conditional on the results of a background check performed by a third party acting on our behalf. For more information on how we handle your data please see our Applicant and Candidate Privacy Policy.

At Google DeepMind we value diversity of experience knowledge backgrounds and perspectives and harness these qualities to create extraordinary impact. We are committed to equal employment opportunity regardless of sex race religion or belief ethnic or national origin disability age citizenship marital domestic or civil partnership status sexual orientation gender identity pregnancy or related condition (including breastfeeding) or any other basis as protected by applicable law. If you have a disability or additional need that requires accommodation please do not hesitate to let us know.