SoC Timing Design EngineerLeader
SoC Timing Design EngineerLeader
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1 Vacancy
Job Description
Reason for Hiring
High performance SoC are key parts to realize automobiles electric and high performance which are so called CASE (Connected Automated Shared Electric). SoC are becoming more larger and complex to meet the demand of more function and high performance. Cost competition is also a key. In the timing design viewpoint developing a large scale complex SoC is required and we want to recruit an innovative engineer.
Were waiting for a engineer who can work with global mindset since were coworking with Vietnam India design site (language:English)
Role Responsibilities
SoC Timing Design Engineer or Leader. Timing design technology development and product development by Static Timing Analysis Timing Constraint design and Logic Synthesis.
- Static Timing Analysis
Timing design by using EDA vendors EDA tool - Timing constraint design
Timing constraint design by using EDA vendors tool and Renesas tool - Logic synthesis:
Logic Synthesis by using EDA vendors tool.
All Static Timing Analysis Timing Constraint design and logic synthesis case will be coworking with oversea design center.
*The full details regarding your position scope as well as any future potential changes in work location and job scope will be provided during the interview process.
What We Offer
In the PhysicalDesign role the manager is also deeply involved in the actual design process leading the of product development and improvement of the development flow. This is an important role in the completion of LSI product design from a position close to the design site.
The process node used is the most advanced node 3nm) for automotive applications. We are proud that the difficulty and satisfaction of digital backend design is at the top level. We collaborate with overseas EDA vendors and design centers and you can participate in the work of a global organization.
What Are We Looking For
- Ability to tackle challenges
- Strong leadership skills
- Capability to see the big picture
- Ability to propose effective solutions
Qualifications :
MUST
- Timing design (Static Timing Analysis Timing Constraint debugging )experience: over 8 year
- English at a communicative level
- Jaoanese at a communicative level
WANT
- Hardware language (ex. VerilogHDL)
- Experience of using English in business
Additional Information :
To Make Our Lives Easier PurposeIoT
To Make Our Lives Easier
- 4
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Remote Work :
No
Employment Type :
Fulltime
Employment Type
Full-time
