Senior Verification Engineer
Senior Verification Engineer
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Job Description
Cambridge UK Fulltime or Parttime Permanent Hybrid
Salary: 65000 to 80000 DOE
We will also consider parttime applications for this role. Please indicate your preferred working schedule in your cover letter.
About us
Riverlanes mission is to make quantum computing useful sooner. From advances in material science to complex chemistry simulation for drug design and discovery quantum computers will help solve some of the worlds most important challenges. Riverlane is building the quantum error correction stack Deltaflow to make this happen. Its a complex problem that requires a range of skills talent and passion.
About the role
You will work with our talented team of hardware designers and embedded software engineers to produce a fully verified trusted and performant solution. With full visibility of the entire stack you will own everything verification related. As a Senior Verification Engineer at Riverlane you will:
- Proactively work with designers and architects to define verification plans based on design specifications. You will own define and track detailed test plans for different blocks and system level.
- Implement scalable testbenches including checkers reference models and coverage groups in SystemVerilog. You will implement selftesting directed and random tests.
- Maintain the design verification environment keeping track of regression coverage metrics and bugs.
You do not need a background in quantum computing! You will learn this along the way...
What you will do
You will work with our talented team of hardware designers and embedded software engineers to produce a fully verified trusted and performant solution. With full visibility of the entire stack you will own everything verification related. As a Senior Verification Engineer at Riverlane you will:
- Proactively work with designers and architects to define verification plans based on design specifications. You will own define and track detailed test plans for different blocks and system level.
- Implement scalable testbenches including checkers reference models and coverage groups in SystemVerilog. You will implement selftesting directed and random tests.
- Maintain the design verification environment keeping track of regression coverage metrics and bugs.
You do not need a background in quantum computing! You will learn this along the way...
Requirements
What we need
- Demonstrable commercial experience in functional verification including ownership of verification planning and strategy.
- A proactive and collaborative person who actively shares feedback and who can independently define the scope of work.
- Proven experience of testbench design with verification frameworks like UVM/OVM.
- Knowledge of SystemVerilog assertion (SVA).
- Exposure to different programming languages such as C C and Python
Even better if
- You have formal verification experience
Benefits
What you can expect from us
- A comprehensive benefits package including annual bonus scheme private medical insurance life insurance a contributory pension scheme (and much more)
- Equity so that our team can share in the longterm success of Riverlane
- 28 days annual leave (plus bank holidays) and enhanced family leave
- A diverse work environment that brings together experts in many fields (including software and hardware development quantum information theory physics maths and many more) and over 20 different nationalities
- A learning environment that encourages individual team and company growth and learning including an annual training and conference budget
How to apply
Please upload a CV and cover letter by clicking Apply. Your cover letter should explain why you are applying for the job and what skills and experience you can bring to the role.
We review CVs as we receive them and interview as soon as we have applications that look like a good match (usually within one week). We do not use closing dates. So please apply as soon as possible to avoid missing out on this role. We advertised this role on 4thApril 2025. If you have any queries please contact.
Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age disability ethnicity gender gender reassignment religion or belief sexual orientation marital or civil partnership status or pregnancy and maternity/paternity.
Studies have shown that women tend to apply to jobs if they meet all or almost all of the requirements whereas men apply even if they meet only some of the requirements. If that sounds like you then please apply we are happy to review your application and let you know if we think you might be a good fit.
If you need any adjustments made to the application or selection process so you can do your best please let us know. We will be happy to help.
Required Experience:
Senior IC
Employment Type
Full-Time
