TSSCI w Poly Digital Verification Engineer- SVA UVM
TSSCI w Poly Digital Verification Engineer- SVA UVM
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Salary Not Disclosed
1 Vacancy
Job Description
All qualified resumes responded to in 24HRs or less
Applicants must be US citizens
All work will be preformed onsite
These are Full time Direct positions Consuting may be an option on a case by case sinerio
Bachelors degree in Electrical Engineering or other STEM (Science Technology Engineering or Mathematics) discipline
12 years of digital verification engineering experience using industry standard simulation tools 10 years with an MS degree; 7 years with PhD)
An additional 5 years of experience can be used in Lieu of a BS degree
Advanced Knowledge of UVM and use of a coveragedriven verification methodology
Experience developing test plans participating in reviews test development and RTL debug
U.S. Citizenship
ACTIVE TS/SCI Clearance with ACTIVE Polygraph required in order to be considered.
Preferred Qualifications:
MS in Electrical Engineering or comparable engineering discipline
Experience with data structures objectoriented programming languages and concepts
Experience with Verification IP integration and/or development
Experience with a coveragedriven verification methodology from planning through closure
Knowledge of industry standard bus or I/O interfaces
Experience with SystemVerilog Assertions (SVA)
FPGA/ASIC design and/or development process experience
Experience with scripting languages (Bash Perl Python Tcl Makefile)
Knowledge of digital signal processing
#CJ
Employment Type
Full Time
