Senior System Digital Design Engineer FM

The goal of the SCE (Secure Connected Edge) team within NXP is to become the leader in its market by leveraging its unique portfolio of IP from NFC and Secure Elements NFC and UHF tags WiFi UWB and Bluetooth products to deliver solutions that are better than the sum of its parts.

NXP is a world leader in security especially for mobile payment applications and continues to drive growth through innovation.

Working in a fast paces mobile environment we are looking for an outstanding System Digital Design Engineer to join our global System Team. This team defines cuttingedge RF/analog systems in the area of PMU mixedsignal (PLL ADC DAC) & radio transceivers (RX TX). Designing chips in advanced process nodes 40nm 28HPC 22FDX our architectures leverage extensively on highspeed & highperformance digital islands embedded in our RF/analog macros. These islands are in essence either controllers calibrations engines DSP functions or critical pieces of the signal paths of our transceivers.

We have an opening for a talented System Digital Design Engineer to take in charge the definition and design of our Digital Islands.

You have an excellent communication skills and proven ability to collaborate across organizational and geographical boundaries. The role might also involve communication with key customers for detailed reviews.

Scope of Responsibilities

As a system digital design engineer in our RF/analog and mixedsignal organization you will be involved in the entireactivity around the definition design and verification of our digital islands. You are interested in solving complex analog problems with digital circuits.

In this context you will work on stateoftheart highly digitized systems including

• DCDC converters (Buck Boost)
• PLLs (APLL DPLL)
• ADCs & DACs
• RF receivers & transmitters

Your responsibilities:

• Contribute to the IP architecture definition (PLL DCDC ADC DAC TX RX) in strong cooperation with the analog team members
• Run upfront feasibility studies that conceptually prove the ability to meet speed (MHz to GHz range) power consumption & area targets of critical digital islands. This requires you are able to quickly compare several digital architectures by running a full digital flow from system definition (simulink SystemC) to synthesis & power analysis during this system definition phase
• Define and design controllers digital/mixedsignal calibration engines or dedicated parts of the signal paths (sample rate converters sigmadelta modulators decoders..
• Take ownership of the system model the RTL design at macro & block level and contribute through various phases of the ASIC/SOC design process including the full verification (including AMS verification in the context of the full mixedsignal IP/subsystem) & documentation
• Early run of physical implementation to assess feasibility & area
• Strongly cooperate with & support the SoC team. Parts of the digital island design (scan backend) might be outsourced to this team

Your Profile:

• MS or higher in Electrical Engineering or equivalent discipline required

• 15 years of relevant experience in Digital Circuit Design. Proficient with Cadence suite
• Strong analytical and debugging skills
• Experience in system modeling (matlab Simulink SystemC)
• Experience in all aspects of RTL design flow fromSpecification/Microarchitecture definition to design and verification Timing Analysis DFT and physical implementation
• Proficient in digital design and handson experience with Verilog/System Verilog RTL coding
• Firm understanding and handson experience on IP Integration RTL signoff tools and CDC/RDC/Lint/Synthesis
• Strong domain knowledge of Clocking Reset System modes Power management
• Scripting languages (Shell TCL PERL Python)
• Analog Behavioral Models (VerilogA VerilogAMS Wreal SystemVerilog EEnet)
• Experience with Multiple Power and Clock domains
• Experience with highspeed (MultiGHz) digital design
• Experience with digital design of signal processing functions as: sample rate converters (integer SRC and arbitrary SRC) FIR filters deltasigma modulators clock recoveries
• Experience with SystemC synthesis tools (Stratus HLS) would be an asset

• Good communication and interpersonal skills working in a highly collaborative team

• SelfDriven with a cando attitude

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