Senior Digital SimulationVerification CAD Engineer
Senior Digital SimulationVerification CAD Engineer
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Job Description
We areSilicon Labs.We are a leader in secure intelligent wireless technology for a more connected world.Our integrated hardware and software platform intuitive development tools unmatched ecosystem and robust support make us the ideal longterm partner in building advanced industrial commercial home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries groweconomiesand improve lives.
Meet the Team
Be part of a highly skilled CAD Engineering team critical to the success of Silicon Labs next generation of innovative product offerings!
Responsibilities
Work with digital design verification engineers across multiple design groups and sites to understand requirements and deliver consistent and uniform solutions throughout the organization
Evaluate new verification tools to assess their integration into existing flows
Define and implement improvements to existing flows to stay ahead of project needs
Provide daytoday support of existing digital verification methodologies
Interface with EDA Vendors ensure that their tools are properly integrated into the Silicon Labs flow. Report any bugs and ensure their timely fix
Create detailed documentation for digital design verification flows at Silicon Labs
Provide creative ways (such as Lunch and Learn Symposium papers etc. to ensure that designers are kept aware of CADsupported flows
Skills You Will Need
Minimum qualifications:
BS or MS in Electrical Engineering or equivalent with 5 years of working in or using Digital frontend simulation and verification tools and flows (e.g. Xcelium Questa Jasper Gold Questa Formal)
Indepth knowledge of Design Verification Tools (Functional and Formal) on how they work the data they produce and the appropriate usecases for each flow
Testbench design (using System Verilog or UVM)
Strong familiarity with Verilog System Verilog VHDL
Familiarity with RTL and Gatelevel simulations
Working knowledge of vendor debug tools (e.g. SimVision Visualizer)
Handson experience in scripting using PERL Makefile TCL and any other scripting languages
Working knowledge of version control tools (e.g. svn git)
The following qualifications will be considered a plus:
Knowledge of Real Number Modeling (VerilogAMS wreal or System Verilog UDN)
Knowledge of CortexM based systems
Familiarity with lowpower designs in multiple power domains (e.g. UPF CPF)
Knowledge of Verification Planning and Management (e.g. Cadence vManager)
Assertionbased verification (e.g. SVA)
Familiarity with AMS simulations
Benefits & Perks
You can look forward to the following benefits:
Great medical (Choice of PPO or Consumer Driven Health Plan with HSA) dental and vision plans
Highly competitive salary
401k plan with match and Roth plan option
Equity rewards (RSUs)
Employee Stock Purchase Plan (ESPP)
Life/AD&D and disability coverage
Flexible spending accounts
Adoption assistance
BackUp childcare
Additional benefit options (Commuter benefits Legal benefits Pet insurance)
Flexible PTO schedule
3 paid volunteer days per year
Charitable contribution match
Tuition reimbursement
Free downtown parking
Onsite gym
Monthly wellness offerings
Free snacks
Monthly company updates with our CEO
We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race religion color national origin gender sexual orientation age marital status veteran status or disability status.
Required Experience:
Senior IC
Employment Type
Full-Time
