Staff ASIC Design Engineer - AI Engine 152880
Staff ASIC Design Engineer - AI Engine 152880
Employer Active
Job Alert
You will be updated with latest job alerts via email
Share
Job Alert
You will be updated with latest job alerts via email
Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
What you do at AMD changes everything
We care deeply about transforming lives with AMD technology to enrich our industry our communities and the world. Our mission is to build great products that accelerate nextgeneration computing experiences the building blocks for the data center artificial intelligence PCs gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the worlds most important challenges. We strive for excellence while being direct humble collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.
AMD together we advance
Staff ASIC Design Engineer AI Engineer 152880
THE ROLE:
AMDXilinx is seeking a capable and motivatedRTL/ASIC design engineer to be part of frontend design team of next generation AI Engine/ML processors.
THE PERSON:
You will take part in design and implementation of highperformance lowpower processorand acceleratorIP for AI/ML applications.
KEY RESPONISIBILITES:
In this role you will:
- Define and specify microarchitecture of processor building blocks based on architecture requirements
- RTL design and debug of complex blocks in Verilog / System Verilog
- Analyze performance and make implementation choices to optimize timing
- Analyze and optimize design for power efficiency and power integrity
- Work with verification and physical design teams to achieve high quality design and successful tape out
- Solve customer problems through innovative enhancements to product architecture/ microarchitecture
- Design and implement underlying clocking infrastructures to ensure implementation tool requirements are met and are optimized for compile time and memory
- Collaborate with crossfunctional teams to solve novel problems across multiple functional areas in development of clocking features and/or algorithms
PREFERRED EXPERIECE:
Strong experience in the following
- ASIC design flow and direct experience with ASIC design in sub20nm technology nodes
- Digital design and experience with RTL design in Verilog/System Verilog
- Circuit timing/STA and practical experience with Prime Time or equivalent tools
- Low power digital design and analysis
- Modern SOC tools including Spyglass Questa CDC Cadence Conformal VCS simulation
Experience in following is highly desired
- Understanding of FPGA architecture and implementation flow
- TCL Perl Python scripting
- Version control systems such as Perforce ICManage or Git
- Strong verbal and written communication skills
- Ability to organize and presentcomplex technical information
- Fluent in working with Linux environment
- Needs to be manually updated.
ACADEMIC CREDENTIALS
BSEE or equivalent and 8years of relevant work experience or MSEE or equivalent with 6 years of experience
LOCATION:San Jose CA
#LIDA1
Requisition Number:152880
Country:United StatesState:CaliforniaCity:San Jose
Job Function:Design
Benefits offered are described here.
AMD does not accept unsolicited resumes from headhunters recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age ancestry color marital status medical condition mental or physical disability national origin race religion political and/or third party affiliation sex pregnancy sexual orientation gender identity military or veteran status. Please click here for more information.
Required Experience:
Staff IC
Employment Type
Full-Time
