Senior IC Design Engineer PLL and Clock Distribution
Senior IC Design Engineer PLL and Clock Distribution
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Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
San Diego CA (onsite/hybrid)
US Citizen or US Permanent Resident (preferred)
FullTime Health Benefits 401K Plan PTO Founder Shares
Requirements:
Highspeed timeinterleaved ADCs (SAR pipeline TDC etc. RF frontend design SerDes miscellaneous functions (other data converters filters amplifiers PLLs power management oscillators etc. in FinFET technologies.
MS with 5 years or PhD with 3 years of experience preferred.
Strong PLL and clock distribution experience is preferred
Javier Leon
cell
www.LinkedIn/in/JavierLeon (are we connected)
Required Experience:
Senior IC
Employment Type
Full Time
