Physical Design Engineer
Physical Design Engineer
Posted on :
05-04-2025
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1 Vacancy
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Job Description
Physical Design Engineer
Fulltime Benefits
Dallas Texas (onsite/hybrid)
US Citizen or US Permanent Resident
Responsibilities:
Super user of industry standard Physical Design Synthesis and Timing Analysis tools
Architect system requirements
Plan budget tools and team effort and champion project needs to ensure milestones and objectives are met
Accountable for physical design implementation of complex lowpower designs including physicalaware logic synthesis DFT floorplan place and route static timing analysis IR Drop EM and physical verification
Leverage or enhance existing digital design flow and solve design and flow issues within Cadence Genus Innovus Tempus
Collaborate effectively with the full ASIC design implementation team with a Humble Hungry and Smart attitude
Required Skills / Experience:
BSEE/MSEE with 5 years of related industry experience
5 years of experience with Cadence digital design tools (Genus Innovus Tempus)
5 years handson experience in high reliability low power VLSI designs
Productionproven experience with Floor planning at Chip Level with Bus/Pin variables Synthesis Place and Route Optimization Parasitic Extraction Static Timing Analysis Low Power Intent (UPF/CPF) Power Analysis IR drop analysis electromigration Physical Verification and Sign Off
Excellent understanding of reliability test and power concepts & design tradeoffs required
Skilled with Verilog/VHDL RTL and able to modify for timing or power closure
Knowledge of MIPI I2S CAN protocols a plus
Basic proficiency with programming languages such as Perl C and TCL
ITAR compliance approval required
#PhysicalDesign
Fulltime Benefits
Dallas Texas (onsite/hybrid)
US Citizen or US Permanent Resident
Responsibilities:
Super user of industry standard Physical Design Synthesis and Timing Analysis tools
Architect system requirements
Plan budget tools and team effort and champion project needs to ensure milestones and objectives are met
Accountable for physical design implementation of complex lowpower designs including physicalaware logic synthesis DFT floorplan place and route static timing analysis IR Drop EM and physical verification
Leverage or enhance existing digital design flow and solve design and flow issues within Cadence Genus Innovus Tempus
Collaborate effectively with the full ASIC design implementation team with a Humble Hungry and Smart attitude
Required Skills / Experience:
BSEE/MSEE with 5 years of related industry experience
5 years of experience with Cadence digital design tools (Genus Innovus Tempus)
5 years handson experience in high reliability low power VLSI designs
Productionproven experience with Floor planning at Chip Level with Bus/Pin variables Synthesis Place and Route Optimization Parasitic Extraction Static Timing Analysis Low Power Intent (UPF/CPF) Power Analysis IR drop analysis electromigration Physical Verification and Sign Off
Excellent understanding of reliability test and power concepts & design tradeoffs required
Skilled with Verilog/VHDL RTL and able to modify for timing or power closure
Knowledge of MIPI I2S CAN protocols a plus
Basic proficiency with programming languages such as Perl C and TCL
ITAR compliance approval required
#PhysicalDesign
Javier Leon
cell
www.LinkedIn/in/JavierLeon (are we connected)
Employment Type
Full Time
Key Skills
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