Asynchronous SRAM IC Design Engineer Contract flexible hours US Citizen or US Permanent Resident
We are seeking an experienced Senior SRAM IC Design Engineer with over 10 years of expertise in custom Asynchronous SRAM design. The ideal candidate will possess specific technical knowledge spanning various process technologies from 180nm to FinFET focusing on intricate highperformance circuits. Key skills include proficiency in sense amp write circuit decoder ATD and redundancy design along with chiplevel architecture and simulation experience. Additionally a solid grasp of SRAM DFM and DFMEA for design risk mitigation and yield enhancement techniques is essential.
Required Skills: Minimum 10 years of expertise in custom digital circuits for SRAM design (Asynchronous required) BSEE/MSEE in Applicable Field with 10 years of IC design experience or equivalent Proficient in Cadence/Synopsys design flow Demonstrated success with latewrite SRAM architectures Capability to develop and deliver design reviews test/characterization plans Understanding of digital analog/mixed signal design (digital front end and RF experience preferred) Track record of technical proficiency in integrated circuit design Comprehensive knowledge of silicon development tools and processes best practices supporting postsilicon efforts for productization Strong communication debugging and analytical skills for complex technical concepts Preferred experience with various manufacturing technologies and design applications
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