drjobs Design Verification Engineer

Design Verification Engineer

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1 Vacancy
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Job Location drjobs

Irvine - USA

Yearly Salary drjobs

$ 166600 - 296300

Vacancy

1 Vacancy

Job Description

At Apple we work every single day to craft products that enrich peoples lives. Do you love working on challenges that no one has solved yet and changing the game We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wideranging group you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apples customers daily. This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of presilicon verification including but not limited to: establishing DV methodology testplan development verification environment development including stimulus and checkers testwriting debug coverage signoff for RTL freeze and tapeout.

Description

In this role you will be responsible for ensuring bugfree first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the microarchitecture You are responsible for developing verification methodology suitable for the IP ensuring a scalable and portable environment. You will get to develop verification environment including all the respective components such as stimulus checkers assertions trackers coverage. Furthermore you will develop verification plans for all features under your care execute verification plans including design bringup DV environment bring up regression enabling features and debug of the test failures. You will also learn to develop block IP and SoC level testbenches track and report DV progress using a variety of metrics including bugs and coverage.

Minimum Qualifications

  • BS degree in technical subject area with minimum 10 years of proven experience

Key Qualifications

Preferred Qualifications

  • Solid knowledge of OOP SystemVerilog and UVM
  • Solid knowledge in developing scalable and portable testbenches
  • Relevant experience with verification methodologies and tools such as simulators waveform viewersBuild and run automation coverage collection gate level simulations
  • Experience with poweraware (UPF) or similar verification methodology
  • Excellent knowledge of one of the scripting languages such as Python Perl TCL
  • Experience with serial protocols such as PCIe or USB parallel protocol such as DDR is a plus but not required
  • Knowledge of formal verification methodology is a plus but not required

Education & Experience

Additional Requirements

Pay & Benefits

  • At Apple base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $166600 and $296300 and your base pay will depend on your skills qualifications experience and location.

    Apple employees also have the opportunity to become an Apple shareholder through participation in Apples discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards and can purchase Apple stock at a discount if voluntarily participating in Apples Employee Stock Purchase Plan. Youll also receive benefits including: Comprehensive medical and dental coverage retirement benefits a range of discounted products and free services and for formal education related to advancing your career at Apple reimbursement for certain educational expenses including tuition. Additionally this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

    Note: Apple benefit compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Employment Type

Full Time

About Company

0-50 employees
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