Senior engineer - High-Speed Signal Integrity
Senior engineer - High-Speed Signal Integrity
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Job Description
We are seeking a Senior Engineer HighSpeed Signal Integrity to drive research in nextgeneration highspeed wireline electrical communication. This role is part of the HighSpeed HighFrequency team within the Board Engineering department (Lab) at our Grenoble Research Center.
You will work closely with our HQ technical team in China to develop cuttingedge highspeed SerDes systems 112 Gbit/s and beyond). You will contribute to the design simulation and analysis of highspeed interconnects and PCBs while shaping the technology roadmap for highspeed signal integrity.
Location: Grenoble Research Center
Salary:per annum (DOE)
Start Date: ASAP
About the GrenoblAbout the Rolee Research Center
Founded in 2019 by the Hardware Engineering Institute of 2012 Laboratories our Grenoble Research Center is home to 30 engineers including PhDs technical experts and scholars from worldrenowned institutions. Our young and dynamic team is dedicated to solving complex challenges in highspeed technologies for the ICT industry.
As we expand our highspeed research team we offer a unique opportunity to work on stateoftheart technologies with a global impact.
Duties and Responsibilities
Research and develop highspeed interconnects (passive channels) for nextgen systems 112Gbps per lane
Highspeed PCB design simulation and signal integrity analysis
Conduct lab verification of highspeed designs
Collaborate with the HQ team in China through technical reviews reporting and project planning
Define the technology roadmap and research strategy for highspeed interconnects
Requirements
Masters degree or PhD preferred in Electrical Engineering Information Technology Communication Engineering or Electromagnetic Science
Extensive experience in highspeed telecom/communication hardware architecture design
Proven track record in 56Gbps product development and delivery
Deep expertise in highfrequency PCB design including impedance control and crosstalk management
Experience in systemlevel simulation (PCB connector and cablelevel analog signal simulation)
Strong understanding of PCB/HDI stackup design fabrication limitations and cost factors
Knowledge of highspeed SerDes architectures (Rx/Tx SerDes PHY equalization techniques CDR DSP challenges)
Preferred Skills
Familiarity with highspeed serial hardware (SerDes ASIC DSP PCB connectors)
Handson expertise in highspeed lab experiments (realtime oscilloscopes VNAs) and simulation correlation
Knowledge of industry standards (IEEE 802.3 OIFCEI InfiniBand CEI224G)
Active participation in conferences and industry events
Passion for technology and innovation with a strong drive to contribute to highspeed signal integrity research
Technical Tools & Work
HighSpeed / HighFrequency Design & Simulation: CST ANSYS HFSS
SI Analysis: ADS Sigrity MATLAB Python
SerDes Modeling & Simulation: Python (preferred) MATLAB VerilogA ADS
Benefits
Work on cuttingedge 112 Gbit/s SerDes systems
Collaborate with a global R&D team
Engage in highimpact research with industry experts
Shape the future of highspeed signal integrity
Apply now to be part of a worldclass research team in highspeed communication!
How to Apply
Please submit your resume and a cover letter detailing your experience and suitability for the role. We look forward to exploring how you can contribute to our teams innovative projects in highspeed interconnection and boardlevel process reliability.
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Employment Type
Full Time
