RTL Design Engineer - Senior
RTL Design Engineer - Senior
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Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
- Responsible for RTL design using Verilog HDL for implementation and debug.
- Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions.
- Responsible for linting and simulation of design. Work with synthesis and backend teams for physical implementation.
- Perform RTL design of digital components in Verilog/systemverilog.
- Analyze/fix Lint and CDC errors of the components.
- Guarantee quality/timely deliverables meeting projects schedule.
- Help to improve/automate design process.
- 715 years relevant experience
- Experience with RTL design integration tasks
- Multiclock domain designs.
- Design constraints for synthesis and static timing analysis.
- Knowledge of frontend RTL design tools and methodologies.
- Knowledge of scripting languages like Perl tcl or cshell
- SOC Design integration tasks such as (RTL integration Simulation Debug Synthesis STA Constraints scripting/automation)
- Creating technical documentations such as Microarchitecture documentation Integration guides
- High speed serial interfaces (such as PCIe CXL etc.)
- Experience with of AXI protocol
- UPF
- Bachelors (required) or Masters in Computer Engineering
Employment Type
Full Time
