RTL Engineer SystemVerilog Specialist

About the job

Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco our investors include Benchmark General Catalyst Peter Thiel Adam DAngelo Larry Summers and Jack Dorsey.

Position: Expert Hardware / RTL Engineer SystemVerilog / Verilog
Type: Contract
Compensation: $110190/hour
Location: Remote
Commitment: 2040 hours/week

Role Responsibilities

• Apply RTL expertise to evaluate technical tasks against real-world professional standards.
• Review intricate code-level situations and provide precise structured written assessments.
• Work inside Docker-based repositories running and interpreting programmatic and CI-style checks to ensure a sound engineering environment.
• Provide clear written rationales explaining your expert judgments.
• Complete well-defined time-bounded tasks with explicit evaluation criteria.

Qualifications

Must-Have

• 5 years of professional or research RTL experience in SystemVerilog or Verilog.
• Hands-on depth in RTL design testbench/UVM verification FPGA or ASIC work and EDA toolchains (Vivado Quartus Synopsys Cadence).
• Comfort working in Linux/Docker-based repo environments and reading automated/CI checks.
• Ability to articulate not just what code does but why its correct or idiomatic clearly in writing.

Preferred

• Engineers from semiconductor telecom defense/aerospace national-lab or academic backgrounds.

Compensation & Legal

• Hourly contractor
• Paid weekly via Stripe Connect

Application Process (Takes 2030 mins to complete)

• Upload resume
• AI interview based on your resume
• Submit form

Resources & Support

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PS: Our team reviews applications daily. Please complete your AI interview and application steps to be considered for this opportunity.